Digital ASIC Design and Verification Engineer

Siliconally is a pure IP company. We develop several different IPs as in-house solutions and sell licenses to our customers. We use an automotive grade engineering process with agile methods. The process starts on system engineering level that breaks down and integrates the sub-IPs for our products with a digital on top integration process.

Our digital team is responsible for the full digital engineering cycle, which consists of breaking down the requirements into capabilities, features, qualities and constraints. For complex solution parts, we start with a lean dev approach to explore the solution and raise the maturity in a round trip process that is tied in sprint time boxes.

Besides all technical knowledge, you should have passion for ASIC design and development.

We work with the standard tool chains from Cadence and Synopsys and you should have experience in creating valuable results with these tools in your specific domain.

Know how in requirements engineering, systems engineering, functional/technical safety, scripting with TCL and Python and some management capabilities are a plus.

Additionally, you should be able to prove your know how in your domain by examples from your studies or professional job experience.

For all of you that are interested in synthesis, physical implementation and sign-off: We don't do that in-house and therefore do not hire engineers with scope on that topic.

•  Support architecture definition of digital blocks according to customer specification
• Support RTL design (VHDL, Verilog) of digital blocks and their system level integration
• Closely work together with RTL2GDS flow experts to optimize digital blocks and support block implementation
• Support chip and block level functional verification
• Implement and maintain regression setups for verification
• Create verification plans and develop verification environments based on Unified Verification Methodology (UVM)
• Support product qualification, testing and ramp-up
• Support methodology team with proposals and implementation of flow and methodology enhancements

• Master’s Degree in Electrical Engineering or Information Technology or similar required
• Knowledge of hardware description languages (VHDL, Verilog) and System Verilog
• Knowledge about synthesis constraints (SDC) and UPF
• Understanding of UVM/OVM concepts and usage or strong motivation to learn concepts for state of the art verification
• Experience in functional verification and creating test concepts and verification environments is a plus
• Self-driven and hands-on way of working
• Good written and oral communication skills in English
• Team-player

We offer an attractive salary package taking your professional work experience and qualification into account. Our full-time employees work 40 h a week with paid over hours. It makes no difference for us, if you more appreciate it working from home or coming to the office, if you enjoy working part time or if you're a workaholic. We are flexible and family friendly.

We work with our team in an open office environment in proximity to the Dresden Technical University. You can reach us via perfect public transportation in the city of Dresden, we have free bicycle garages for our cyclists and of course we also have free parking's for the colleagues, that drive by car. For the colleagues that join us in our office, we offer free beverages and fresh fruits.
A company paid free Membership in Urban Sports Club allows your access to over 7.000 sports possibilities to stay strong and healthy.

We highly appreciate the application of female candidates and take care for equal payment for the same work.

If you have any further questions, please contact us via Email.

For all Applicants from Asia, please be ready to relocate to Dresden Germany.

We are looking forward to your application.